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| NJU26100 Series NJU26100 Series Hardware Specification General Description This document describes the NJU26100 Series common hardware specifications. This document is applied to the NJU26101 up to the NJU26199. The individual function is described in the each data sheet. Please refer to the each data sheet to find the detail functions. The firmware commands are described in the each firmware document. Package Hardware Specification NJU26100 Series * 24bit Fixed-point Digital Signal Processing * Maximum System Clock Frequency : 38MHz * Digital Audio Interface : 3 Input ports / 3 Output ports * Master / Slave Mode * Master Mode MCK :1/2 fclk, 1/3 fclk ex. MCK = 384Fs(1/2) or MCK = 256Fs(1/3) at fclk=768Fs * Two kinds of micro computer interface I2C bus (standard-mode/100kbps) Serial interface (4 lines: clock, enable, input data, output data) * Power Supply : 2.5V ( 3.3V Input tolerant ) * Package : QFP32-R1 AD1/SDIN AD2/SSb NJU26100 Series DSP ARITHMETIC UNIT SERIAL AUDIO INTERFACE BCKO LRO SERIAL OUT 24-BIT x 24-BIT MULTIPLIER ALU SERIAL OUT SERIAL OUT SERIAL IN SDO0 SDO1 SDO2 SDI0 SDI1 SDI2 BCKI LRI SCL/SCK SDA/SDOUT SERIAL HOST INTERFACE PROGRAM CONTROL RESETb MCK XI XO TIMING GENERATOR ADDRESS GENERATION UNIT SERIAL IN SERIAL IN DELAY RAM DATA RAM FIRMWARE ROM GPIO AND CONFIGURATION INTERFACE GPIO0 GPIO1 Ver.2005-02-24 -1- NJU26100 Series Pin Configuration VDDR VDDR VDDC VDDC VSSR 24 VSSR 23 VSSC VSSC 22 21 20 19 18 17 SDI0 SDI1 SDI2 LRI BCKI MCK BCKO LRO 25 GPIO1 VSSC VDDC RESETb VSSO XO XI VDDO 16 26 15 27 14 NJU26100 Series 28 29 30 31 32 1 13 12 11 10 9 2 3 4 5 6 7 8 SDO2 SDO1 SDO0 GPIO0 SCL/SCK SDA/SDOUT AD1/SDIN AD2/SSb Pin Description Pin Description No. Symbol I/O Description No. Symbol I/O Description 1 SDO2 O Audio Data Output CH2 17 VDDC -Core Power Supply +2.5V 2 SDO1 O Audio Data Output CH1 18 VDDC -Core Power Supply +2.5V 3 SDO0 O Audio Data Output CH0 19 VSSC -Core GND 4 GPIO0 I/O General Purpose IO 20 VSSC -Core GND 2 5 SCL/SCK I I C Clock / Serial Clock 21 VDDR -I/O Power Supply +2.5V 6 SDA/SDOUT I/O I2C I/O / Serial Output 22 VDDR -I/O Power Supply +2.5V 7 AD1/SDIN I I2C Address / Serial Input 23 VSSR -I/O GND 8 AD2/SSb I I2C Address / Serial Enable 24 VSSR -I/O GND 9 VDDO -OSC Power Supply +2.5V 25 SDI0 I Audio Data Input CH0 10 XI I X'tal Clock Input 26 SDI1 I Audio Data Input CH1 11 XO O OSC Output 27 SDI2 I Audio Data Input CH2 12 VSSO -OSC GND 28 LRI I LR Clock Input 13 RESETb I RESET (active Low) 29 BCKI I Bit Clock Input 14 VDDC -Core Power Supply +2.5V 30 MCK O Master Clock Output 15 VSSC -Core GND 31 BCKO O Bit Clock Output 16 GPIO1 I/O General Purpose IO 32 LRO O LR Clock Output *1 I : Input, O : Output, I/O : Bi-directional *2 SDI0, SDI1, SDI2, SDO0, SDO1, SDO2, GPIO0, GPIO1 are different by any function. Refer to each datasheet. -2- Ver.2005-02-24 NJU26100 Series 1. Electric Characteristics 1.1 Absolute Maximum Ratings Table1-1 Absolute Maximum Ratings (VSSO=VSSC=VSSR=0V, Ta=25C) Parameter Supply Voltage XI Input Voltage Input Pin Voltage Symbol VDD Vx(OSC) Vx(IN) Rating 0 to 3.05 -0.3 to VDD -0.3 to 3.6 Units V V V Power Dissipation PD 0.3 W Storage Temperature Tstg -40 to +125 C 1 * They apply SCL/SCK, AD1/SDIN, AD2/SSb, RESETb, SDI0, SDI1, SDI2, LRI, and BCKI pin. It applies to GPIO0 (SEL1) pin of NJU26100 series except NJU26150. However, it applies to SDA/SDOUT pin at the time of I2C mode operation. Ver.2005-02-24 -3- NJU26100 Series 1.2 Electric Characteristics Table1-2 Electric Characteristics (VDDO=VDDC=VDDR=2.5V, VSSO=VSSC=VSSR=0V, Ta=25C) Parameter Operating VDD Voltage Operating Current Operating Temperature Recommended Operating Temperature High Level Input Voltage (XI) High Level Input Voltage Low Level Input Voltage High Level Input Current High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage Input Capacitance Input Rise/Fall transition Time Clock Frequency Ext.System Clock Duty Cycle 1 Symbol VDD IDD TOPR TOPRR VIH(OSC) VIH VIL IIH IIH(pd) IIL VOH VOL CIN tr / tf fOSC rEC Test Condition VDDO, VDDC, VDDR pin fOSC=36.864MHz Min. 2.25 -40 Typ. 2.5 40 25 25 5 50 Max. 2.75 85 70 VDD 3.3 0.5 +10 300 +10 0.4 100 38.0 52.5 Units V mA C C VDDO=VDDC=VDDR =2.5V XI pin VSS=VSSO=VSSC=VSSR VIN =3.3V expect for GPIO pin VIN =3.3V GPIO pin Only VIN=VSSO=VSSC=VSSR IOH=-2mA IOH=-100A IOL=2mA except for SCL/SCK, SDA/SDOUT, AD1/SDIN, AD2/SS pin*1 XI pin XI pin -10 2.0 2.0 VSS -10 100 -10 VDD -0.4 VDD -0.1 47.5 V V V A A A V V pF ns MHz % * The tr / tf of these pins are specified separately. *2 All input / input-and-output pins serve as the Schmidt trigger input except for XI pin. VDDR Input pin VDDC Output pin VDDR XI VSSR pin XI / XO pin (XI, XO) VSSC Input pin (GPIO0, SCL/SCK, SDA/SDOUT, AD1/SDIN, AD2/SSb, RESETb, GPIO1, SDI0, SDI1, SDI2, LRI, BCKI pin) VDDC VDDO XO pin VSSO VSSC Output pin (SDO0, SDO1, SDO2, GPIO0, *3SDA/SDOUT, GPIO1, MCK, BCKO, LRO pin) Fig.1- 1 I/O Equivalent Circuits *3 SDA becomes Open-Drain at the time of the output of I2C. -4- Ver.2005-02-24 NJU26100 Series 2. Clock and Reset The NJU26100 Series XI pin requires the system clock that should be related to the sample frequency Fs. The XI/XO pins can generate the system clock by connecting the crystal oscillator or the ceramic resonator. When the external oscillator is connected to XI/XO pins, check the voltage level of the pins. Because the maximum input voltage level of XI pin is deferent from the other input or bi-directional pins. The maximum voltage-level of XI pin equals to VDD. To initialize the NJU26100 Series, RESETb pin should be set Low level during some period. After some period of Low level, RESETb pin should be High level. This procedure starts the initialization of the NJU26100 Series. To select I2C bus or 4-Wire serial bus, some level should be supplied to GPIO0 pin (SEL1 pin). When GPIO0 pin (SEL1 pin)="Low", I2C bus is selected. When GPIO0 pin (SEL1 pin)="High", 4-Wire serial bus is selected. The level of GPIO0 pin (SEL1 pin) is checked by the NJU26100 Series in 1 m sec after RESETb pin level goes to "High". After the power supply and the oscillation of the NJU26100 Series becomes stable, RESETb pin should be kept Low-level more than tRESETb period. VDD XI OSC unstable OSC stable tRESETb RESETb Fig. 2- 1 Reset Timing Table 2- 1 Reset Time Symbol tRESETb Time 1s Notice : Please consult with manufacture of crystal oscillator / ceramic resonator enough in use of these parts. NJRC would not take the responsibility on the external parts of clock generating. Ver.2005-02-24 -5- NJU26100 Series 3. Audio Clock Audio data samples must be transferred in synchronism between all components of the digital audio system. That is, for each audio sample originated by an audio source there must be one and only one audio sample processed by the NJU26100 Series and delivered to the D/A converters. To accomplish this, one device in the system is selected to generate the audio sample rate; the remaining devices are designated to follow this sample rate. The device that generates the audio sample rate is called the MASTER device; all devices following this sample rate are called SLAVE(s). LR, BCK and MCK should be synchronized. This is described in next section. When the NJU26100 Series is in MASTER mode, the NJU26100 Series system clock should be 768 multiples of the sampling frequency (Table3-1). When the NJU26100 Series is in SLAVE mode, NJU26100 Series system clock should be from 768 multiples of the sampling frequency up to the maximum operating frequency. 3.1 System Clock Three types of clock signals are included in the serial audio interface. Two of the clock signals LR (LRI and LRO) and BCK (BCKI and BCKO) establish data transfer on the serial data lines. The third clock, MCK, is not associated with serial data transfer but is required by delta-sigma A/D and D/A converters. The frequency of the LR clock is, by definition, equal to the digital audio sample rate, Fs. BCK and MCK operate at multiples of the LR clock rate. Therefore the signals LR, BCK and MCK must be locked, that is, they must be generated or derived from a single frequency reference. In SLAVE mode, the NJU26100 Series dose not generate MCK clock. Table 3-1 Sampling Frequency and BCK, MCK, XI Clock Signal LR BCK(32Fs) BCK(64Fs) MCK(256Fs) MCK(384Fs) XI Multiple Frequency 1Fs 32Fs 64Fs 256Fs 384Fs 768Fs 32kHz 32kHz 1.024MHz 2.048MHz 8.192MHz 12.288MHz 24.576MHz 44.1kHz 44.1kHz 1.4112MHz 2.822MHz 11.289MHz 16.934MHz 33.8688MHz 48kHz 48kHz 1.536MHz 3.072MHz 12.288MHz 18.432MHz 36.864MHz SDIx SDOx BCKI LRI BCKO LRO MCK CLOCK DIVIDER MAS TER SLAVE XI XO Oscillator Fig. 3-1 MASTER / SLAVE Mode -6- Ver.2005-02-24 NJU26100 Series 4. Audio Interface The serial audio interface carries audio data to and from the NJU26100 Series. Industry standard serial data formats of I2S, MSB-first left-justified or MSB-first right-justified are supported. These serial audio formats define a pair of digital audio signals (stereo audio) on each data line. Two clock lines, BCK (bit clock) and LR (left/right word clock) establish timing for serial data transfers. The NJU26100 Series serial audio interface includes three data input lines, SDI0, SDI1 and SDI2, and three data output lines, SDO0, SDO1 and SDO2, as shown in the figure below. The input serial data is selected by the firmaware command. The number of these serial audio interfaces depends on the DSP function. Check the each data sheet. The NJU26100 Series has a pair of left/right clock lines (LRI and LRO) and a pair of bit clock lines (BCKI and BCKO). Clock inputs BCKI and LRI are used to accept timing signals from an external device when the NJU26100 Series is operating in SLAVE clock mode. The BCKO, LRO and MCK, system clock output, are provided for delta-sigma A/D and D/A converters when the NJU26100 Series operates in MASTER mode. In SLAVE mode, the output of BCKO and LRO are the buffered output of BCKI and LRI. The output of MCK is fixed to Low level in SLAVE mode. Serial Data Inputs SDI0 SDI1 SDI2 SDO0 SDO1 SDO2 Serial Data Outputs NJU26100 Serial Clock Inputs BCKI LRI BCKO LRO MCK Serial Clock Outputs System clock for A/D, D/A converters (DSP MASTER mode only) Fig. 4-1 Serial Audio Interface The NJU26100 Series can exchange data using any of three industry-standard digital audio data formats: I2S, MSB-first Left-justified, or MSB-first Right-justified. The three serial formats differ primarily in the placement of the audio data word relative to the LR clock. Left-justified format places the most-significant data bit (MSB) as the first bit after an LR transition. I2S format places the most-significant data bit (MSB) as the second bit after an LR transition (one bit delay relative to left-justified format). Right-justified format places the least-significant data bit (LSB) as the last bit before an LR transition. Clock LR (LRI, LRO) marks data word boundaries and clock BCK (BCKI, BCKO) clocks the transfer of serial data bits. One period of LR defines a complete stereo audio sample and thus the rate of LR equals the audio sample rate (Fs). All formats transmit the stereo sample left channel first. Note that polarity of LR is opposite in I2S format (LR:LOW = Left channel data) compared to Left-Justified or Right-Justified formats. 4.1 Audio Data Format Ver.2005-02-24 -7- NJU26100 Series The number of BCK clock must follow the serial data format. If the BCK clock is not enough, the right sound are not produced. Set serial data format for the adequate mode that A/Ds, D/As or Codecs reqire. The NJU26100 Series supports serial data format which includes 32(32Fs) or 64(64Fs) BCK clocks. This serial data format is applied to both MASTER and SLAVE mode. 4.2 Serial Audio Data Transmitting Diagram LRI, LRO BCKI, BCKO M SB LSB 32 Clocks M SB 32 Clocks LSB 23 Left Channel Right Channel SDI, SDO 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 4-2 Left-Justified Data Format 64Fs, 24bit Data LRI, LRO BCKI, BCKO M SB Left Channel Right Channel LSB 32 Clocks M SB 32 Clocks LSB SDI, SDO 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 4-3 Right-Justified Data Format 64Fs, 24bit Data LRI, LRO BCKI, BCKO M SB Left Channel Right Channel LSB 32 Clocks M SB 32 Clocks LSB SDI, SDO 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 4-4 I2S Data Format 64Fs, 24bit Data LRI, LRO BCKI, BCKO M SB Left Channel Right Channel LSB 32 Clocks M SB 32 Clocks LSB 19 SDI, SDO 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 4-5 Left-Justified Data Format 64Fs, 20bit Data * The 24bit data is always outputted to a SDO0 pin in the format of figure 4-5 to figure 4-10. -8- Ver.2005-02-24 NJU26100 Series LRI, LRO BCKI, BCKO M SB LSB 32 Clocks M SB 32 Clocks LSB Left Channel Right Channel SDI, SDO 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 4-6 Right-Justified Data Format 64Fs, 20bit Data LRI, LRO BCKI, BCKO M SB Left Channel Right Channel LSB 32 Clocks M SB 32 Clocks LSB SDI, SDO 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 4-7 I2S Data Format 64Fs, 20bit Data LRI, LRO BCKI, BCKO M SB Left Channel Right Channel LSB 32 Clocks M SB 32 Clocks LSB 17 SDI, SDO 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 4-8 Left-Justified Data Format 64Fs, 18bit Data LRI, LRO BCKI, BCKO M SB Left Channel Right Channel LSB 32 Clocks M SB 32 Clocks LSB SDI, SDO 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 4-9 Right-Justified Data Format 64Fs, 18bit Data LRI, LRO BCKI, BCKO M SB Left Channel Right Channel LSB 32 Clocks M SB 32 Clocks LSB SDI, SDO 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 4-10 I2S Data Format 64Fs, 18bit Data Ver.2005-02-24 -9- NJU26100 Series LRI, LRO BCKI, BCKO M SB Left Channel Right Channel LSB M SB 16 Clocks 16 Clocks LSB SDI, SDO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 4-11 Left-Justified Data Format 32Fs, 16bit Data LRI, LRO BCKI, BCKO M SB Left Channel Right Channel LSB M SB 16 Clocks 16 Clocks LSB SDI, SDO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 4-12 Right-Justified Data Format 32Fs, 16bit Data LRI, LRO BCKI, BCKO M SB Left Channel Right Channel LSB M SB 16 Clocks 16 Clocks LSB SDI, SDO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 4-13 I2S Data Format 32Fs, 16bit Data - 10 - Ver.2005-02-24 NJU26100 Series 4.3 Serial Audio Timing Table 4-1 Serial Audio Input Timing Parameters (VDDO=VDDC=VDDR=2.5V, VSSO=VSSC=VSSR=0V, Ta=25C) Parameter BCKI Frequency ** BCKI Period ** Low Pulse Width High Pulse Width BCKI to LRI Time ** LRI to BCKI Time ** Data Setup Time Data Hold Time * * Symbol fBCKI tSIL tSIH TSLI tLSI tDS tDH Test Condition Min 0.9 85 85 40 40 40 40 Typ. Max 4.0 Units MHz ns ns ns ns ns * It is the regulation to BCKI in slave mode and to BCKO in master mode. ** It is the regulation in slave mode. LRI tSIH tSIL tSLI tLSI BCKI tDS tDH SDI0,1 Fig. 4-14 Serial Audio Input Timing Ver.2005-02-24 - 11 - NJU26100 Series Table 4-2 Serial Audio Output Timing Parameters (VDDO=VDDC=VDDR=2.5V, VSSO=VSSC=VSSR=0V, Ta=25C) Parameter BCKO to LRO Time * Data Output Delay Symbol tSLO tDOD Test Condition CL:LRO, BCKO, SDO=25pF Min -20 - Typ. - Max 20 20 Units ns ns * It is the regulation in master mode. LRO tSLO BCKO tDOD SDO Fig. 4-15 Serial Audio Output Timing Table 4-3 Serial Audio Clock Timing Parameters (In slave mode) (VDDO=VDDC=VDDR=2.5V, VSSO=VSSC=VSSR=0V, Ta=25C) Parameter Clock Output Delay (LRI --> LRO) Clock Output Delay (BCKI --> BCKO) Symbol tPDL tPDB Test Condition CL:LRO,BCKO, SDO=25pF Min - Typ. - Max 20 20 Units ns ns LRI LRO tPDL BCKI BCKO tPDB Fig. 4-16 Serial Audio Clock Timing (In slave mode) - 12 - Ver.2005-02-24 NJU26100 Series 5. Host Interface The NJU26100 Series can be controlled via Serial Host Interface (SHI) using either of two serial bus formats: 4-Wire serial bus or I2C bus. Data transfers are in 8 bit packets (1 byte) when using either format. The SHI operates only in a SLAVE fashion. A host controller connected to the interface always drives the clock (SCL / SCK) line and initiates data transfers, regardless of the chosen communication protocol. Table 5-1 Serial Host Interface Pin Description Pin No. 5 6 Symbol (I2C / Serial) SCL/SCK SDA/SDOUT 4-Wire Serial bus Format Serial Clock Serial Data Output I2C bus Format Serial Clock Serial Data (Bi-directional) I2C bus address Bit1 I2C bus address Bit2 7 AD1/SDIN Serial Data Input 8 AD2/SSb SLAVE Select Note : SDA /SDOUT pin is a bi-directional open drain. SDA /SDOUT output is normal CMOS output in case of 4-Wire Serial bus mode and SSb="Low". SDA /SDOUT output is Hi-Z state in case of 4-Wire Serial bus mode and SSb="High". This pin requires a 4.7k pull-up resister in both 4-Wire serial and I2C bus mode. 5.1 4-Wire Serial Interface The serial host interface can be configured for 4-Wire Serial bus communication by setting GPIO0 pin (*SEL1 pin)="High" during the Reset initialization sequence. SHI bus communication is full-duplex; a write byte is shifted into the SDIN pin at the same time that a read byte is shifted out of the SDOUT pin. Data transfers are MSB first and are enabled by setting the Slave Select pin Low (SSb = 0). Data is clocked into SDIN on rising transitions of SCK. Data is latched at SDOUT on falling transitions of SCK except for the first byte (MSB) which is latched on the falling transitions of SSb. SDOUT is Hi-Z in case of SSb = "High". SDOUT is CMOS output in case of SSb = "Low". SDOUT needs a pull-up resistor when SDOUT is Hi-Z. * It excepts NJU26150. Refer to each data sheet. Ver.2005-02-24 - 13 - NJU26100 Series Table 5-2 4-Wire Serial Interface Timing Parameters (VDDO=VDDC=VDDR=2.5V, VSSO=VSSC=VSSR=0V, Ta=25C) Parameter Input Data Rising Time Input Data Falling Time Serial Clock Rising Time Serial Clock Falling Time Serial Strobe Rising Time Serial Strobe Falling Time Serial Clock High Duration Serial Clock Low Duration Serial Clock Period Serial Strobe Setup Time Serial Strobe Hold Time Serial Strobe Low Duration Serial Strobe High Duration Input Data Setup Time Input Data Hold Time Output Data Delay (From SSb) Output Data Delay (From SCK) Output Data Hold Time Output Data Turn off Time (Hi-Z) a SDIN Symbol tMSDr tMSDf tMSCr tMSCf tMSSr tMSSf tMSCa tMSCn tMSCc tMSSs tMSSh tMSSa tMSSn tMSDis tMSDih tMSDos tMSDo tMSDoh tMSDov Timelines a-b a-b d-e f-g p-q m-n e-f g-h e-i n-e j-q n-p q-r b-e e-c n-o,CL=25pF g-k(data-6), CL=25pF g-k(data-7) q-l Min. 50 50 250 100 30 40 20 20 0 - Typ. - 1.0 Max. 100 100 100 100 100 100 50 50 40 Units ns ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns - b c 7 d ef 6 gh i 5 1 0 j SCK SDOUT Hi-Z m n o 7 k 6 5 1 0 Note (3) Hi-Z l SSb MSB LSB p q r Fig. 5-1 4-Wire Serial Interface Timing Note : *1 When the data-clock is less than 8 clocks, the input data is shifted to LSB side and is sent to the DSP core at the transition of SSb="High". *2 When the data-clock is more than 8 clocks, the last 8 bit data becomes valid. *3 After sending LSB data, SDOUT transmits the MSB data which is received via SDIN until SSb becomes "High". *4 SDOUT is Hi-Z in case of SSb = "High". SDOUT is CMOS output in case of SSb = "Low". SDOUT needs a pull-up resistor to prevent SDOUT from becoming floating level. - 14 - Ver.2005-02-24 NJU26100 Series When the NJU26100 Series is configured for I2C bus communication in GPIO0 pin (*SEL1 pin)="Low", the serial host interface transfers data to the SDA pin and clocks data to the SCL pin. SDA is an open drain pin requiring an external 4.7k pull-up resistor. AD1 and AD2 pins are used to configure the seven-bit SLAVE address of the serial host interface. This offers additional flexibility to a system design by four different SLAVE addresses of the NJU26100 Series. An address can be arbitrarily set up by the AD1, 2 pins. The I2C address of AD1, 2 is decided by connection of AD1, 2 pins. The I2C address should be the same level of AD1, 2 pins. The real I2C address is described in the each data sheet. Refer to the each data sheet. * It excepts NJU26150. Refer to each data sheet. 5.2 I2C Bus Table 5-3 I2C Bus SLAVE Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 1 1 1 AD2*1 AD1*1 R/W *1 The SLAVE address bit is 0 when ADx-pin is low level. The SLAVE address bit is 1 when ADx-pin is high level. The figure on the following page shows the basic timing relationships for transfers. A transfer is initiated with a START condition, followed by the SLAVE address byte. The SLAVE address consists of the seven-bit SLAVE address followed by a read/write (R/W) bit. When an address with an effective serial host interface is detected, the acknowledgement bit which sets a SDA line to Low in the ninth bit clock cycle is returned. The R/W bit in the SLAVE address byte sets the direction of data transmission until a STOP condition terminates the transfer. R/W = 0 indicates the host will send to the NJU26100 Series while R/W = 1 indicates the host will receive data from the NJU26100 Series. SDA 1-7 8 9 1-7 8 9 SCL S Start Address R/W ACK Data ACK P Stop Fig. 5-2 I2C Bus Format In case of the NJU26100 Series, only single-byte transmission is available. The serial host interface supports "Standard-Mode (100kbps)" I2C bus data transfer. Ver.2005-02-24 - 15 - NJU26100 Series Table 5-4 I2C Bus Interface Timing Parameters (VDDO=VDDC=VDDR=2.5V, VSSO=VSSC=VSSR=0V, Ta=25C) Parameter SCL Clock Frequency Start Condition Hold Time SCL "Low" Duration SCL "High" Duration Start Condition Setup Time Data Hole Time Data Setup Time Rising Time Falling Time Stop Condition Setup Time Bus Release Time Symbol fSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tBUF Standard Mode Min Max 0 100 4.0 4.7 4.0 4.7 0 3.45 250 1000 300 4.0 4.7 Units kHz s s s s s ns ns ns s s SDA tBUF tR tF tHD:STA SCL tHD:STA tLOW P S tHD:DAT tHIGH t SU:DAT Sr tSU:STA tSU:STO P Fig. 5-3 I2C Bus Timing I C License 2 Purchase of I2C components of New Japan Radio Co. ,Ltd or one of sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard specification as defined by Philips. - 16 - Ver.2005-02-24 NJU26100 Series 6. Package Dimensions (EIAJ : QFP032-P-0707-1) Weight 0.2g (TYP) [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. Ver. 1.14 Ver.2005-02-24 - 17 - |
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